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Application Note 9725
Layout and Power Supplies
The HI5746EVAL1 evaluation board is a four layer board
with a layout optimized for the best performance of the ADC.
Included in the application note are electrical schematics of
the evaluation board circuitry, a components layout, a
components part list and views of the various board layers
that make up the printed wiring board. The user should feel
free to copy the layout in their application. Refer to the
components layout and the evaluation board electrical
schematics for the following discussions.
The HI5746 A/D converter has separate analog and digital
supply and ground pins to keep digital noise out of the
analog signal path. The evaluation board provides separate
low impedance analog and digital ground planes. Since the
analog and digital ground planes of the evaluation board are
connected together at a single point where the power
supplies enter the board, DO NOT tie the grounds together
back at the power supplies.
The analog and digital supplies are also kept separate on the
evaluation board and should be driven by clean linear
regulated supplies. The power supplies can be hooked up
with external wires to the holes marked +5VAIN, +5VA1IN, -
5VAIN, +5VDIN, +5VD1IN and +5VD2IN. +5VDIN, +5VD1IN
and +5VD2IN are digital supplies and should be returned to
DGND. +5VAIN, +5VA1IN and -5VAIN are the analog supplies
and should be returned to AGND. Table 1 lists the operational
supply voltages for the evaluation board. Single supply
operation of the converter is possible but the overall
performance of the converter may degrade.
TABLE 1. EVALUATION BOARD POWER SUPPLIES
between V REF - and analog ground. This allows the user the
option of supplying only the +2.5V V REF + voltage reference
with the +2.0V V REF - being generated internally by the
voltage division action of the input structure.
The HI5746 is tested with V REF - equal to +2.0V and V REF +
equal to +2.5V yielding a fully differential analog input voltage
range of ± 0.5V.
In order to minimize overall converter noise it is recommended
that adequate high frequency decoupling be provided at both
of the reference voltage input pins, V REF + and V REF -.
The V REF + and V REF - reference voltage generation circuitry
on the evaluation board consists of a Intersil ICL8069 +1.2V
bandgap voltage reference (D1) along with operational
ampli?ers (U3 and U4) both operating in a non-inverting
variable gain con?guration that is utilized to generate the
reference voltages for the HI5746. The reference voltages,
V REF + and V REF -, are set at the factory to the proper
voltage levels required by the HI5746. Variable resistor VR1
is used to adjust V REF + to +2.5V and variable resistor VR2
is used to adjust V REF - to +2.0V.
Operation of the converter with a single +2.5V V REF +
reference voltage can be demonstrated by simply removing
R20 from the V REF - generation circuit. This opens the path
between the V REF - operational ampli?er (U4) output and the
V REF - input of the HI5746 while still providing decoupling at
the converter V REF - voltage reference input pin.
Sample Clock Driver
In order to ensure rated performance of the HI5746, the duty
cycle of the sample clock should be held at 50%. It must also
POWER
SUPPLY
+5VAIN
+5VA1iN
-5VAIN
+5VDIN
+5VD1IN
+5VD2IN
NOMINAL
VALUE
5.0V ± 5%
5.0V ± 5%
-5.0V ± 5%
5.0V ± 5%
5.0V ± 5%
5.0V ± 5% /
3.0V ± 10%
CURRENT
(TYP) FUNCTION(S) SUPPLIED
121mA Analog Input and Reference
Voltage Generator Op Amps,
Bandgap Reference
30mA A/D AV CC
120mA Analog Input and
Reference Voltage
Generator Op Amps,
Bandgap Reference
5mA Sample Clock Generator,
D0-D9 D-FF
13mA A/D DV CC1
3mA A/D DV CC2
have low phase noise and operate at standard TTL logic levels.
It can be difficult to find a low phase noise generator that will
provide a 40MHz squarewave at TTL logic levels.
Consequently, the HI5746EVAL1 evaluation board is designed
with a logic inverter (U7) acting as a voltage comparator to
generate the sampling clock for the HI5746 when a sinewave
(< ± 1.5V) is applied to the CLK input of the evaluation board.
The sample clock sinewave is AC coupled into the input of the
inverter and a discrete bias tee is used to bias the sinewave
around the trigger level of the inverter’s input. A potentiometer
(VR3) varies the DC bias voltage added to the sinewave input
allowing the user to adjust the duty cycle of the sampling clock
to obtain the best performance from the ADC and to evaluate
Reference Voltage Generator Circuit
The HI5746 is designed to accept two external reference
voltage sources at the V REF input pins. Typical operation of
the converter requires V REF + to be set at +2.5V and V REF - to
be set at 2.0V. However, it should be noted that the input
structure of the V REF + and V REF - input pins consists of a
resistive voltage divider with one resistor of the divider
(nominally 500 ? ) connected between V REF + and V REF - and
the other resistor of the divider (nominally 2000 ? ) connected
3-4
the effects of sample clock duty cycle on the performance of the
converter. The trigger level for the sample clock input to the
HI5746 converter is approximately 1.5V. Therefore, the duty
cycle of the sampling clock should be measured around the
1.5V trigger level at the HI5746 sample clock input pin.
The sinewave to logic level comparator drives a series of
additional inverters that provides isolation between the four
sample clocks used on the evaluation board. One clock is
used to drive the converter sample clock input pin, a second
clock is used to drive the digital output data (D0-D9) D-type
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